1. Field of the Invention
The present invention relates generally to semiconductor manufacturing. More specifically, the present invention relates to an etching process to be performed during semiconductor manufacturing.
2. Description of the Related Art
Etching processes are commonly and repeatedly carried out during the manufacture of a semiconductor wafer (“wafer”). As is well known to those skilled in the art, there are two types of etching processes: wet etching and dry etching. Dry etching is typically performed using either a capacitively coupled or an inductively coupled plasma etching apparatus.
An etching process is often used to define a particular feature on a surface of the wafer. One or more dimensions of the feature may be considered a critical dimension. As features become smaller and more closely spaced on the surface of the wafer, critical dimension uniformity across the wafer becomes a greater concern. In particular, critical dimension trim becomes more of a critical path operation to be examined for uniformity. Critical dimension trim refers to the amount of lateral etch that occurs on a side of the feature from which the critical dimension is measured. Therefore, uniformity of critical dimension trim influences the adequacy of both the size of features and the spacing between features.
Etching processes to remove oxide and nitride materials have been traditionally performed using a dielectric etcher. The dielectric etcher is capacitively coupled and, as such, does not provide adequate uniformity across the wafer with respect to critical dimension trim. Additionally, the dielectric etcher does not allow for control of critical dimension trim during the etching process.
In view of the foregoing, there is a need for a method and apparatus for providing uniform trim of oxide and nitride materials that are relevant to critical dimensions of features distributed across the wafer.